搜索资源列表
RTL
- verilog的学习很重要的教程，有很大的好处。-verilog tutorial learning is important, a great advantage.
i2c
- I2C verilog代码，支持master和slave方式，内置CPU接口-I2C verilog RTL code， support master and slave mode
rtl
- 基于verilog的FPGA新型跑马灯程序设计-led run
I2C_Verilog_Model
- 该源程序包是I2C的Verilog语言模型，包括以下4个部分：RTL源代码，测试平台，软件仿真代码，说明文件。-This source package is I2C bus model based on Verilog language. It has the following 4 parts: RTL code, testbench, sofeware simulating code, help document.
SD_Controller_Verilog
- 该程序包是SD卡/MMC卡控制器SDC的verilog语言包，它包括以下4部分：RTL源代码，测试平台，软件仿真文件，说明文件。-This source package is the SD card and MMC card controler model based on the Verilog language. It has the following 4 parts: RTL language, testbench, software simulating files and help
ALU
- verilog硬件仿真，实现32-bit RISC微处理器的算数逻辑单仿真元(ALU),实现加减运算、逻辑运算、移位运算。仿真级别为RTL级。-verilog hardware simulation, to achieve 32-bit RISC microprocessor arithmetic logic one simulation element (ALU), to achieve addition and subtraction operations, logic operations
rtl
- led and 7segment with verilog
ai32-RTL
- verilog code analog output board
interpolation-filer-rtl
- synthesizable verilog rtl implemetation of interpolation filter, for both asic and fpga. 64x interpolation. interp_filter.v interp_first.v interp_second.v interp_third.v upsample.v
mpci32-verilog
- 一个32BIT 33/66MHz PCI CORE，verilog 的RTL CODEs-pci ipcore writen by verilog
Verilog-digital-system-design-RTL-synthesis-testb
- verilog book. RTL sysnthesis testbech
rtl
- Verilog 蜂鸣器唱歌程序 同时可以显示音调大小-The Verilog buzzer singing program
verilog-coding-rules
- Verilog HDL可综合RTL级代码设计规范及风格-Verilog HDL RTL level code design specifications and style
verilog
- verilog数字系统设计-rtl综合测试平台与验证 书中源码-verilog Digital System Design-rtl test platform verification book source
Principles-of-Verifiable-RTL-Design
- 本书主要以HDL（verilog/vhdl）为例，详细讲述了在IC DESIGN FLOW中 Verification 以及Test的设计思想、方法和技巧，涵概了测试的各个方面， 是目前进行IC设计的同仁们最为推荐的一本宝典-Book HDL (verilog/vhdl), a detailed account of the IC DESIGN FLOW, Verification and Test of design ideas, methods and techniques, and
two_dimensional_fast_hartley_transform_latest.tar
- RTL Verilog code to perform Two Dimensional Fast Hartley Transform (2D-FHT) for 8x8 points. Presented algorithm is FHT with decimation in frequency domain.
rtl.tar
- This RTL of Router by uisng verilog-This is RTL of Router by uisng verilog
IEEE-Std-1364.1-2002-Verilog-RTL-Synthesys
- IEEE Std 1364.1-2002 Verilog RTL Synthesys
RTL
- verilog编写的关于使用MENTOR的MBISTArchitect进行momery的自测试代码，包含测试算法模型，SRAM,ROM模型-verilog prepared by the use of MBISTArchitect for momery MENTOR self-test code, including test algorithm model, SRAM, ROM model
8051-Verilog
- 8051的Verilog源代码，包含说明文件，RTL文件，工程等-8051 Verilog source code, including documentation, RTL files, engineering, etc.